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This talk will provide a detailed tour of the hardware architecture behind AMD's NextGen GPUs - unveiling the intimate details that make AMD's Graphics Core Next (GCN) architecture so capable at both graphics and compute workloads. Special consideration will be taken to explain how the GCN architecture can best be exploited by graphics engineers working on next-gen game engines.
This talk will provide attendees with an architectural level of detail and understanding rarely available in the public domain. The GCN compute and functional units and their capabilities will be discussed in detail. Instruction arbitration and scheduling, memory hierarchy and layout, cache design, graphics and compute dispatch and control flow, as well as higher level constructs will all be discussed.
This talk aims to deliver information at a level that is accessible to all; however, those possessing a basic understanding of hardware architecture (memory hierarchies, arithmetic logic units, instruction scheduling, SIMD vs. SIMT, etc.) will likely find much additional benefit in the low-level details presented. Experience with assembly language programming is not necessary, but will also prove useful, as examples illustrating the process of optimizing shaders for GCN's compute units will be examined via HLSL presented side-by-side with native GCN assembly.